What This Document Is
This is a detailed assignment description for ECE 4680, Computer Organization and Design, at Wayne State University. Specifically, it outlines the requirements for Lab Assignment 3, focusing on practical application of Verilog and MIPS CPU design principles. It details a project involving the modification and testing of a multi-cycle MIPS CPU implementation. The assignment centers around expanding the functionality of an existing CPU design and verifying its operation through simulation.
Why This Document Matters
This assignment is crucial for students enrolled in Computer Organization and Design courses. It’s designed for those seeking to solidify their understanding of computer architecture concepts through hands-on experience. Students will benefit from carefully reviewing this document *before* beginning the lab work to ensure a clear understanding of expectations and grading criteria. It’s particularly valuable when you’re ready to translate theoretical knowledge into a working hardware description language (HDL) implementation and testbench. Understanding the submission guidelines and academic integrity policies detailed within is also essential.
Common Limitations or Challenges
This document provides a comprehensive overview of the assignment, but it does *not* include the actual Verilog code for the base CPU design, nor does it provide step-by-step solutions to the implementation challenges. It assumes a foundational understanding of Verilog, MIPS instruction sets, and CPU architecture. It also doesn’t offer debugging assistance or pre-built test cases – students are expected to develop their own testbenches and verify the correctness of their implementations independently.
What This Document Provides
* A clear statement of the assignment’s objectives and learning outcomes.
* Specific instructions regarding individual or paired work.
* Detailed submission requirements, including file naming conventions and digital drop box procedures.
* A firm policy statement regarding academic honesty and plagiarism.
* Guidance on the initial setup and memory loading process for the CPU simulation.
* A description of the required signals to monitor during simulation for verification.
* A grading rubric outlining the criteria for evaluation.
* References to supporting resources, such as a sample Verilog design available online.
