What This Document Is
This document details a project assignment for COMSCI 258F, Physical Design Automation of VLSI Systems, at UCLA. It outlines a practical exercise focused on refining circuit placement, a crucial step in the design of Very Large Scale Integrated (VLSI) circuits. The project centers around optimizing for both wirelength and cell density, key considerations for efficient and manufacturable chip layouts. It’s a substantial undertaking designed to provide hands-on experience with industry-relevant techniques.
Why This Document Matters
This assignment is essential for students enrolled in the course who aim to deepen their understanding of physical design principles. It’s particularly valuable for those interested in pursuing careers in VLSI design, CAD tool development, or related fields. Students will benefit from carefully reviewing this document *before* beginning the project to fully grasp the scope, requirements, and available resources. It serves as the foundational guide for a significant portion of the course grade.
Topics Covered
* Standard cell based circuit placement
* Wirelength optimization techniques
* Cell density overflow mitigation
* Combinatorial optimization applied to VLSI layout
* Netlist representation and manipulation
* VLSI layout program development
* Global placement refinement
* Scaled HPWL (Half Perimeter Wire Length) considerations
What This Document Provides
* A clear project objective focused on density-aware global placement refinement.
* Information on required input file formats (including .aux, .nodes, .pl, .mets, .scl, and .iwts).
* Statistics for several benchmark circuits to be used for testing.
* Details regarding a provided netlist parser and associated data structures (Vertex, Hedge, Pin, Hgraph).
* Descriptions of key classes and member values within the parser for accessing circuit information.
* A link to download necessary project testcases, parser source code, and utility tools.
