What This Document Is
This is a lab exercise guide for ELENG 141, Introduction to Digital Integrated Circuits, at UC Berkeley. Specifically, it focuses on the crucial stage of post-layout simulation in the integrated circuit design flow. This exercise builds upon prior knowledge of schematic design and layout creation, guiding students through the verification processes necessary to ensure a successful chip implementation. It’s designed to be used in conjunction with industry-standard Electronic Design Automation (EDA) tools.
Why This Document Matters
This resource is essential for students enrolled in ELENG 141 who are working on their integrated circuit design projects. It’s particularly valuable when transitioning from theoretical design to physical realization. Understanding these verification steps is critical for identifying and correcting errors *before* fabrication, saving significant time and resources. Students will benefit from this guide during the lab portion of the course, as they implement these techniques on their own designs.
Topics Covered
* Circuit Extraction from Layout
* Design Rule Checking (DRC) verification – a review of prior concepts
* Layout Versus Schematic (LVS) comparison
* Utilization of industry-standard EDA tools for verification
* Interpreting simulation results to validate design integrity
* Understanding topological equivalence between schematic and layout
What This Document Provides
* A structured workflow for post-layout simulation.
* Guidance on configuring and running essential EDA tools.
* Information on interpreting the output of circuit extraction and LVS processes.
* Context for understanding the importance of each verification step in the overall design process.
* Details on how to identify potential discrepancies between the intended schematic and the physical layout.
