What This Document Is
This document outlines the requirements for Phase 2 of the term project in ELENG 141, Introduction to Digital Integrated Circuits at UC Berkeley. It details the tasks involved in translating a previously designed digital circuit – a priority encoder – into a physical layout. This phase focuses on the practical implementation of circuit design principles, moving beyond schematic design into the complexities of physical realization. It serves as a guide for students to demonstrate their understanding of the entire design flow.
Why This Document Matters
This project phase is crucial for students aiming to solidify their understanding of integrated circuit design. It’s particularly beneficial for those preparing for careers in VLSI design, microchip fabrication, or related fields. Students will benefit from carefully reviewing this document *before* beginning the layout process, and referring back to it throughout the implementation and analysis stages. Successfully completing this phase demonstrates a practical grasp of how theoretical designs translate into tangible hardware.
Topics Covered
* Physical Layout Design Principles
* MAX Layout Editor Usage (including hierarchical extraction)
* Design Rule Checking and Error Resolution
* Well and Contact Implementation
* Supply and Ground Rail Distribution
* Layout Versus Schematic (LVS) Verification
* Post-Layout Performance Analysis (Energy and Delay)
* Impact of Physical Design on Circuit Performance
* Report Writing and Technical Communication
What This Document Provides
* Detailed specifications for the physical layout of a priority encoder.
* Guidelines for a strategic approach to layout design, emphasizing modularity and regularity.
* Instructions for submitting extracted SPICE input decks for analysis.
* A clear grading scheme outlining the weight of this phase within the overall project.
* Specific requirements for the project report, including page limits and content guidelines.
* Expectations regarding performance comparison between pre- and post-layout simulations.
