This document is a completed lab assignment for CSE 120, Digital Design Fundamentals at Arizona State University. Specifically, it’s the answer sheet for Lab 2, focusing on the design and testing of multiplexers and decoders using Altera’s online circuit development tools. It’s intended as a submission from a student demonstrating their understanding of basic digital logic concepts.
This lab assignment is valuable for students enrolled in CSE 120 as it provides a practical application of the theoretical concepts covered in the course. It’s used to assess a student’s ability to translate digital logic designs into functional circuits and verify their behavior through simulation. It’s completed during the lab portion of the course, reinforcing learning through hands-on experience.
This completed assignment serves as an example of expected work, but does not provide instruction on *how* to complete the lab. It highlights common challenges students faced, such as understanding the application of Verilog code for symbol file creation, and debugging circuit behavior. It does not include the original lab instructions or a comprehensive explanation of the underlying digital logic principles.
This document provides completed responses for tasks involving building and testing: a 1-bit 2:1 multiplexer, a 4-bit 2:1 multiplexer, a 7-Segment Decoder Symbol File, a NOT/NEG circuit, an AND/ADD circuit, and a complete ALU circuit. It also includes screenshots of the Quartus circuit designs and simulation timing diagrams. This preview *does not* include the original lab assignment instructions, the Verilog code used for the decoder, or a detailed explanation of the design process.
