What This Document Is
This coursework assignment is designed for students enrolled in an upper-level Microfabrication Technology course (ELENG 143) at the University of California, Berkeley. It presents a series of layout design problems central to integrated circuit fabrication. The assignment focuses on applying established design rules to create physical layouts of fundamental CMOS circuits. It builds upon theoretical knowledge and requires practical application of those principles.
Why This Document Matters
This assignment is crucial for students aiming to develop a strong understanding of the practical considerations involved in transforming circuit schematics into manufacturable integrated circuit layouts. It’s particularly beneficial for those pursuing careers in VLSI design, microelectronics, or related fields. Students will benefit from working through these problems as they reinforce core concepts and prepare for more advanced design projects. It’s best utilized after completing foundational coursework in CMOS device physics and layout principles.
Topics Covered
* MOSFET Layout Design
* NMOS Inverter Layout
* NOR Gate Layout
* Design Rule Application
* Contact Hole Placement & Optimization
* Silicon-on-Sapphire (SOS) Technology Considerations
* Minimum Geometry Layout Techniques
* Layout Scaling and Graph Paper Usage
What This Document Provides
* Detailed problem statements requiring physical layout design.
* Circuit diagrams and schematic cross-sections for reference.
* A set of established design rules specific to the EE143 course.
* Guidance on layout scaling and the use of provided graph paper.
* A discussion prompt regarding the impact of different fabrication technologies on design rule sets.
* References to required reading materials for background information.
